Polysilicon is a material commonly used as a conductor in the fabrication of integrated circuits (“I.C.s”). Polysilicon is particularly desirable for forming gates of metal-oxide-semiconductor (“MOS”)-type field-effect transistors (“FETs”). Polysilicon gates for sub-micron FETs are often defined from a layer of polysilicon in a two-step process because of physical limitations of photomask techniques.
First, a layer of photoresist is formed over the polysilicon layer, exposed to light through a photomask, and developed to remove the undesired areas of photoresist. The minimum dimension that can be patterned in the photoresist depends on the wavelength of the light used to expose the photoresist, among other factors. The developed photoresist over the polysilicon gate areas is baked and then anisotropically etched. This etching reduces the size of the photoresist, resulting in a finer linewidth than the pre-etched photoresist. Thus, a linewidth that is narrower than what could be produced by photolithography alone is transferred to the photoresist pattern.
Etching reduces both the length and the width of the gate photoresist. A narrow width is desirable to provide a short channel length to the eventual FET; however, for proper FET operation, the gate extends beyond the active region of the FET to form what is commonly known as a “poly endcap.” Providing a poly endcap avoids shorting of the FET terminals. The gate photoresist pattern is then made longer in the direction it extends beyond the active region to compensate for the length that will be lost during the etching process in order to maintain the desired overlap, which is the amount the gate extends beyond the active area to overlap the substrate. This undesirably increases the distance between FETs on a wafer, reducing the packing density.
Thus, it is desirable to selectively trim the linewidth of a photoresist pattern and improve packing density.